Fractional-N phase lock loop (PLL) allows synthesis of a signal (for example, for use as a timing and synchronization signal, e.g., a clock signal) having frequency resolution that is a fraction of a reference frequency. Unlike integer-N PLLs, fractional-N PLLs allow synthesis of frequencies which are a fraction of the reference frequency. Thus, a fractional-N PLL can use a higher reference frequency than an integer-N PLL for the same frequency resolution. A high reference frequency typically results in a faster settling time for fractional-N PLLs and better suppression to the noise coming from the PLL oscillator.
One type of fractional-N PLL uses a single divider, at any given time, that changes dynamically between fractional-number values N and N+1 such that the “average” division becomes the desired fraction. Because of the switching between a division value of N and N+1, quantization error are introduced by the modulator used to generate the fractional division ratio. Though loop filters are used to suppress the quantization noise, for certain applications, for example, for a wide-band PLL, the quantization noise can dominate the PLL phase noise and cause large spurs.
There is a need for fractional-N PLLs with improved operational performance